Integrated circuits such as programmable integrated circuits often contain volatile memory elements in the form of static random access memory (SRAM) cells. Volatile memory elements such as SRAM cells are typically based on cross-coupled inverters (i.e., latches). The memory elements are arranged in arrays. In a typical array, data lines are used to write data into and read data from the memory elements. Address lines are used to select which of the memory elements are being accessed.
Certain applications require the memory elements to have dual-port capabilities (i.e., memory elements that include two ports each of which is used to perform a read or write operation). To support dual-port operations, memory elements are typically formed in an eight-transistor configuration. For example, a conventional dual-port memory element includes two cross-coupled inverters and first and second pairs of access transistors. The first pair of access transistors is coupled to the cross-coupled inverters to serve as a first read/write port, whereas the second pair of access transistors is coupled to the cross-coupled inverters to serve as a second read/write port. The conventional eight-transistor (8T) dual-port memory cell arranged in this way, however, can occupy more than double the area of a conventional six-transistor (6T) single-port memory cell.
In an effort to reduce area of dual-port memory circuitry, techniques have been developed that permit the use of 6T memory elements in providing synchronous dual-port functionality (i.e., both ports are controlled using a single clock). For example, double-clocking techniques involve accessing the memory element during a high clock phase (to fulfill requests associated with a first port) and during a low clock phase (to fulfill requests associated with a second port). Double-clocking memory access, however, limits memory performance and cannot be used to support asynchronous dual-port operation (i.e., operation that involves using two separate clock signals with different clock frequency and/or phase to control the two ports).